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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT161 Presettable synchronous 4-bit binary counter; asynchronous reset
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
FEATURES * Synchronous counting and loading * Two count enable inputs for n-bit cascading * Positive-edge triggered clock * Asynchronous reset * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT161 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT161 are synchronous presettable binary counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable
74HC/HCT161
input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: 1 fmax = -------------------------------------------------------------------------------------------------t P(max) (CP to TC) + t SU (CEP to CP)
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER tPHL/ tPLH propagation delay CP to Qn CP to TC MR to Qn MR to TC CET to TC maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 19 21 20 20 10 44 3.5 33 HCT 20 24 25 26 14 45 3.5 35 ns ns ns ns ns MHz pF pF UNIT Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V
fmax CI CPD
December 1990
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Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PIN DESCRIPTION PIN NO. 1 2 3, 4, 5, 6 7 8 9 10 14, 13, 12, 11 15 16 SYMBOL MR CP D0 to D3 CEP GND PE CET Q0 to Q3 TC VCC NAME AND FUNCTION asynchronous master reset (active LOW) clock input (LOW-to-HIGH, edge-triggered) data inputs count enable input ground (0 V) parallel enable input (active LOW) count enable carry input flip-flop outputs terminal count output positive supply voltage
74HC/HCT161
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
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Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
74HC/HCT161
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS OPERATING MODE MR reset (clear) parallel load count hold (do nothing) Note 1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH). H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition X = don't care = LOW-to-HIGH CP transition L H H H H H X X X CP X X X h I X CEP X X X h X I CET X I I h h h PE X I h X X X Dn L L H count qn qn Qn L L
(1) (1) (1)
OUTPUTS TC
L
December 1990
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Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
74HC/HCT161
Fig.5 State diagram.
Fig.6
Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two; inhibit.
December 1990
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Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
74HC/HCT161
Fig.7 Logic diagram.
December 1990
6
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH propagation delay CP to Qn propagation delay CP to TC propagation delay MR to Qn propagation delay MR to TC propagation delay CET to TC output transition time 61 22 18 69 25 20 63 23 18 63 23 18 33 12 10 19 7 6 80 16 14 80 16 14 100 20 17 80 16 14 100 20 17 22 8 6 19 7 6 19 7 6 25 9 7 30 11 9 max. 190 38 32 215 43 37 210 42 36 220 44 37 150 30 26 75 15 13 100 20 17 100 20 17 125 25 21 100 20 17 125 25 21 -40 to +85 min. max. 240 48 41 270 54 46 265 53 45 275 55 47 190 38 33 95 19 16 120 24 20 120 24 20 150 30 26 120 24 20 150 30 26 -40 to +125 min. max. 285 57 48 325 65 55 315 63 54 330 66 56 225 45 38 110 22 19 ns UNIT
74HC/HCT161
TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.8
tPHL/ tPLH
ns
Fig.8
tPHL
ns
Fig.9
tPHL
ns
Fig.9
tPHL/ tPLH
ns
Fig.10
tTHL/ tTLH
ns
Figs 8 and 10
tW
clock pulse width HIGH or LOW master reset pulse width; LOW removal time MR to CP set-up time Dn to CP set-up time PE to CP
ns
Fig.8
tW
ns
Fig.9
trem
ns
Fig.9
tsu
ns
Fig.11
tsu
ns
Fig.11
December 1990
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Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. tsu set-up time CEP, CET to CP hold time Dn, PE, CEP, CET to CP 170 34 29 0 0 0 47 17 14 -14 -5 -4 13 40 48 max. -40 to +85 min. max. 215 43 37 0 0 0 3.6 18 21 -40 to +125 min. 255 51 43 0 0 0 3.0 15 18 max. ns UNIT
74HC/HCT161
TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.12
th
ns
Figs 11 and 12
fmax
maximum clock pulse 4.6 frequency 23 27
MHz
Fig.8
December 1990
8
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types
74HC/HCT161
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT MR CP CEP Dn CET PE
UNIT LOAD COEFFICIENT 0.95 1.10 0.25 0.25 0.75 0.30
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL tPHL tPHL/ tPLH tTHL/ tTLH tW tW trem propagation delay CP to Qn propagation delay CP to TC propagation delay MR to Qn propagation delay MR to TC propagation delay CET to TC output transition time clock pulse width HIGH or LOW master reset pulse width; LOW removal time MR to CP 16 20 20 +25 typ. 23 28 29 30 17 7 7 10 6 -40 to +85 max. min. 43 48 46 51 35 15 20 25 25 max. 54 60 58 64 44 19 24 30 30 -40 to +125 min. max. 65 72 69 77 53 22 ns ns ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.8 Fig.8 Fig.9 Fig.9 Fig.10 Figs 8 and 10 Fig.8 Fig.9 Fig.9 UNIT VCC (V) WAVEFORMS TEST CONDITIONS
December 1990
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Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
Tamb (C) 74HCT SYMBOL PARAMETER min. tsu tsu tsu th set-up time Dn to CP set-up time PE to CP set-up time CEP, CET to CP hold time Dn, PE, CEP, CET to CP 18 30 40 0 +25 typ. 8 17 17 -7 -40 to +85 max. min. 23 38 50 0 max. -40 to +125 min. 27 45 60 0 max. ns ns ns ns UNIT
74HC/HCT161
TEST CONDITIONS VCC (V) 4.5 4.5 4.5 4.5 WAVEFORMS
Fig.11 Fig.11 Fig.12 Figs 11 and 12
fmax
maximum clock pulse 23 frequency
41
18
15
MHz
4.5
Fig.8
December 1990
10
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
AC WAVEFORMS
74HC/HCT161
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9
Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master reset to clock (CP) removal time.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times.
December 1990
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Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary counter; asynchronous reset
74HC/HCT161
The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input PE.
The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.12 Waveforms showing the CEP and CET set-up and hold times.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
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